REV. A
8
ADM1027
SERIAL BUS INTERFACE
Control of the ADM1027 is carried out using the serial System
Management Bus (SMBus). The ADM1027 is connected to this
bus as a slave device, under the control of a master controller.
The ADM1027 has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high,
the ADM1027 will have a default SMBus address of 0101110
or 0x5C. If more than one ADM1027 is to be used in a system,
then each ADM1027 should be placed in address select mode
by strapping Pin 13 low on power-up. The logic state of Pin 14
then determines the devices SMBus address.
Table I. ADM1027 Address Select Mode
Pin 13 State
Pin 14 State
Address
0
Low (10 kW to GND) 0101100 (0x58)
0
High (10 kW pull-up)
0101101 (0x5A)
1
Dont Care
0101110 (0x5C)
(default)
ADM1027
14
13
ADDR_SEL
PWM3/ADDR_EN
V
CC
10k
ADDRESS = 0x5C
Figure 2. Default SMBus Address = 0x5C
ADM1027
14
13
ADDR_SEL
PWM3/ADDR_EN
10k
ADDRESS = 0x58
Figure 3. SMBus Address = 0x58 (Pin 14 = 0)
The device address is sampled and latched on the first valid
SMBus transaction, so any attempted addressing changes made
thereafter will have no immediate effect.
The facility to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus (for example, if more than one
ADM1027 is used in a system).
Once the SMBus address has been assigned, these pins return
to their original function. However, since the circuits required
to set up the SMBus address are unworkable with the PWM
and TACH circuits, it would require the use of muxes to switch
in and out the correct circuit at the correct time.
ADM1027
ADDR_SEL
PWM3/ADDR_EN
ADDRESS = 0x5A
14
13
V
CC
10k
Figure 4. SMBus Address = 0x5A (Pin 14 = 1)
ADM1027
14
13
ADDR_SEL
PWM3/ADDR_EN
V
CC
10k
DO NOT LEAVE ADDR_EN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES
NC
Figure 5. Unpredictable SMBus Address if Pin 13
is Unconnected
Care should be taken to ensure that Pin 13 (PWM3/
ADDR_EN) is either tied high or low. Leaving Pin 13
floating could cause the ADM1027 to power up with an
unexpected address.
Note that if the ADM1027 is placed into address select mode,
Pins 13 and 14 can be used as their alternate functions once
address assignment has taken place (PWM3, TACH4). Care
should be taken using muxes to connect in the appropriate circuit
at the appropriate time.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus the R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to
it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low to high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop conditions
are established. In write mode, the master will pull the
data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the 10th clock
pulse, then high during the 10th clock pulse to assert a
stop condition.
Rev. 3 | Page 8 of 56 | www.onsemi.com
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